freesics
At easics, our years of innovative design work have led us to develop a suite of software tools that streamline our workflow for digital ASIC and FPGA design.
In the spirit of collaboration and technological advancement, we have open sourced two of these tools.
Through freesics, we invite you to access these tools, enhancing your projects and workflows, just as they have ours.
CRC Tool
The CRC Tool is a robust generator for RTL (Register Transfer Level) code that calculates Cyclic Redundancy Checks (CRC) codes. This tool is indispensable for anyone needing reliable data verification within their digital systems.
Customizable Parameters: Set your own polynomial and define the number of input data bits to suit the specific needs of your design.
Flexibility in Output: Choose between VHDL or Verilog output styles to seamlessly integrate with your projects.
Ariadne
Ariadne is the go-to tool for generating structural RTL hierarchy levels, designed to simplify and automate the process of digital ASIC and FPGA design, and make it less error prone.
While writing RTL, your design contains two parts. One is the core functionality which you want to focus on. The other part consists of the structural connections between all blocks. Ariadne helps you automate the second part.
Automated Structure Creation: Automatically generate wrapper levels and establish connections between modules.
Signal Propagation: Facilitate the propagation of extra signals, ensuring that all parts of your system communicate effectively without manual intervention.
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and we will deliver the best solution
based on your needs
easics nv
diestsevest 32 box 2b
3000 leuven, belgium
diestsevest 32 box 2b
3000 leuven, belgium
vat: BE 0444.501.015